A typical integrated circuit (IC) chip is a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned (e.g., photolithographically) to define the shapes that combine to form devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer.
Typically, an electrical design for a circuit (e.g., a logic gate (a book or a block), a latch or a higher level function (a macro)) is converted into a digital-graphical representation or layout of the equivalent physical circuit with shapes on design levels corresponding to desired IC shapes. A typical IC design is formed from a number of such basic elements or books that are placed on a representation of the chip (floorplan) and connected together (wired) for the desired final function. After placing and wiring, the layers of the corresponding chip layout are converted to a series of masks, each holding the intended pattern for one of the chip layers. Each mask is used to pattern one of the layers onto the chip. Ideally, each formed shape exactly matches its corresponding design shape. In reality, printing the mask, printing the mask pattern in photo-resist and forming the photo-resist shape pattern in a semiconductor layer (also known as patterning the layer), produces a somewhat altered the final product, e.g., with rounded corners, notches may close, lines or spaces may narrow and etc. Thus typically, the physical design shapes (layout) are biased to anticipate compensate, somewhat, for these changes.
One such source of such changes from design to final product arises from printing shapes in close proximity to one another. Proximity effects occur on a mask, for example, because light printing one shape in photo-sensitive material (i.e., when the material is exposed in the form of the printed shape) also diffuses to neighboring material. So, as each shape is printed, light diffuses to previously printed neighboring shapes, e.g., onto the entire printed shape or onto an edge, overexposing the shape and/or causing it to print slightly out of focus, i.e., causing what is known as proximity effects. Since it is impossible to determine what shapes will be effected by what other shapes (i.e., what shapes are in close proximity of each other) until after place and wire, design shapes have not been biased for proximity effects until after place and wire, when the distance between neighboring shapes is certain. So, after physical design, the design data is prepared (also known as dataprep) for the mask making tool. During dataprep biases are computed for each chip shape and added to physical design shapes to compensate for proximity effects and improve the match between design and mask/wafer shapes.
Unfortunately, a typical state of the art IC design may have thousands, millions and perhaps billions of shapes on each layer. Consequently, proximity correcting all of the shapes on each of the layers can be a daunting task, consuming a tremendous amount of computing resources for each layer, e.g., it may take 440 CPU hours (more than 18 days of dedicated computer time) in a state of the art high performance server. So, the turnaround time for dataprep of a single such mask layer on a typical state of the art high performance server may be months. Prior solutions to mitigate this turn around time include parallel computing and resorting to more efficient correction algorithms. However, using even the most advanced algorithms and the most powerful servers, it may still take more than a CPU week to complete proximity correction for a single chip. Thus, dataprep on a single design can clog a foundry that is meant to process several chip designs in that week.
Thus, there is a need for improved dataprep techniques for complex IC designs and more particularly, for more efficient methods of proximity correcting design data.